NDLI: A concept of a novel edge termination technique: Junction termination (RJT)

Content Provider	IEEE Xplore Digital Library
Author	Honda, S. Fujii, R. Kawakami, T. Fujioka, S. Narazaki, A. Motonami, K.
Copyright Year	2010
Description	Author affiliation: Renesas Semiconductor Engineering Corp., 997 Miyoshi Koshi, Kumamoto, 861-1197, Japan (Fujioka, S.) \|\| Power Semiconductor Device Development Department, Mitsubishi Electric Corporation, 997 Miyoshi Koshi, Kumamoto, 861-1197, Japan (Honda, S.; Narazaki, A.; Motonami, K.) \|\| Advanced technology R&D center, 997 Miyoshi Koshi, Kumamoto, 861-1197, Japan (Kawakami, T.) \|\| Manufacturing Engineering Center, 997 Miyoshi Koshi, Kumamoto, 861-1197, Japan (Fujii, R.)
Abstract	This paper presents a novel junction termination technique, named Recess Junction Termination (RJT), for power devices. This new junction termination improves the breakdown voltage of a planar junction by a silicon recess located to create a positive bevel, which reduces the peak of electric field. The RJT can reduce a thermal budget for the RESURF (REduced SURface Field) layer by the silicon recess, and has compatibility with a fine-pitch process due to a planarization process using Chemical Mechanical Polish (CMP) treatments. After numerous simulations to optimize the structure parameters, we have succeeded in obtaining sufficient blocking capabilities of pn-RJT-diodes, the voltage ratings of which are from 75 V to 1700 V.
Starting Page	111
Ending Page	114
File Size	328622
Page Count	4
File Format	PDF
ISBN	9781424477180
ISSN	19460201
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-06
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Inst of Elec Eng of Japan
Subject Keyword	Silicon Planarization Boron Voltage Substrates Power semiconductor devices Power engineering and energy Surface treatment Fabrication Costs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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