NDLI: The influence of the layout on the ESD performance of HV-LDMOS

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The influence of the layout on the ESD performance of HV-LDMOS

Content Provider	IEEE Xplore Digital Library
Author	Jian-Hsing Lee Hung-Der Su Chien-Ling Chan Yang, D. Chen, J.F. Wu, K.M.
Copyright Year	2010
Description	Author affiliation: Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan City, Taiwan (Yang, D.; Chen, J.F.) \|\| Technology Development Division, Richtek Technology Corporation, Chubei City, Taiwan (Hung-Der Su; Chien-Ling Chan) \|\| HV Program, R&D/TSMC, HsinChu City, Taiwan (Wu, K.M.)
Abstract	The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
Starting Page	303
Ending Page	306
File Size	981488
Page Count	4
File Format	PDF
ISBN	9781424477180
ISSN	19460201
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-06
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Inst of Elec Eng of Japan
Subject Keyword	Electrostatic discharge Testing Cities and towns Voltage Implants Stress Power semiconductor devices DH-HEMTs Microelectronics Research and development
Content Type	Text
Resource Type	Article

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