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Content Provider | IEEE Xplore Digital Library |
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Author | Yedinak, J. Probst, D. Dolny, G. Challa, A. Andrews, J. |
Copyright Year | 2010 |
Description | Author affiliation: Fairchild Semiconductor Corporation, Salt Lake City, Utah USA (Probst, D.; Challa, A.; Andrews, J.) || Fairchild Semiconductor Corporation, Wilkes Barre, PA USA (Yedinak, J.; Dolny, G.) |
Abstract | Power MOSFET designs have been moving to higher performance particularly in the medium voltage area. (60V to 300V) New designs require lower Specific On-resistance while not sacrificing Unclamped Inductive Switching (UIS) capability or increasing turn-off losses. Two charge balance technologies currently address these needs, the PN junction and the Shielded Gate Charge Balance device topologies. This paper will study the impact of drift region as well as other design parameters that influence the shielded gate class of charge balance devices. The optimum design for maximizing UIS capability and minimizing the impact on other design parameters such as R and switching performance are addressed. It will be shown through TCAD simulation one can design devices to have a stable avalanche point that is not influenced by small variations within a die or die-to-die that result from normal processing. Finally, measured and simulated data will be presented showing a fabricated device with near theoretical UIS capability. |
Starting Page | 333 |
Ending Page | 336 |
File Size | 795656 |
Page Count | 4 |
File Format | |
ISBN | 9781424477180 |
ISSN | 19460201 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2010-06-06 |
Publisher Place | Japan |
Access Restriction | Subscribed |
Rights Holder | Inst of Elec Eng of Japan |
Subject Keyword | MOSFET circuits Voltage Doping Medical simulation Silicon Power semiconductor switches Contact resistance Costs Power semiconductor devices Design optimization |
Content Type | Text |
Resource Type | Article |
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