NDLI: Impact of an LPT(II) concept with Thin Wafer Process Technology for IGBT's vertical structure

Content Provider	IEEE Xplore Digital Library
Author	Nakamura, K. Oya, D. Saito, S. Okabe, H. Hatade, K.
Copyright Year	2009
Description	Author affiliation: Power Device Works, Mitsubishi Electric Corporation, Fukuoka, 819-0192, Japan (Nakamura, K.; Oya, D.; Saito, S.; Hatade, K.) \|\| Advanced Technology R&D Center, Mitsubishi Electric Corporation, Fukuoka, 819-0192, Japan (Okabe, H.)
Abstract	In this paper, for the first time, 600 ∼ 6500 V IGBTs utilizing a new vertical structure of “Light Punch-Through (LPT) (II)” with Thin Wafer Process Technology demonstrate high total performance with low overall loss and high safety operating area (SOA) capability. This collector structure enables a wide position in the trade-off characteristics between on-state voltage (V(sat)) and turn-off loss (E) without utilizing any conventional carrier lifetime technique. In addition, this device concept achieves a wide operating junction temperature (@218 ∼ 423 K) of IGBT without the snap-back phenomena (≤298 K) and thermal destruction (≥398 K). From the viewpoint of the high performance of IGBT, the breaking limitation of any Si wafer size, the proposed LPT(II) concept that utilizes an FZ silicon wafer and Thin Wafer Technology is the most promising candidate as a vertical structure of IGBT for the any voltage class.
Starting Page	295
Ending Page	298
File Size	752223
Page Count	4
File Format	PDF
ISBN	9781424435258
ISSN	1943653X
DOI	10.1109/ISPSD.2009.5158060
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-14
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Insulated gate bipolar transistors Voltage Charge carrier lifetime Semiconductor optical amplifiers Diodes Research and development Performance loss Electrical safety Safety devices Temperature
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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