NDLI: High frequency 700V PowerBrane LIGBTs in 0.35µm bulk CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Trajkovic, T. Udugampola, N. Pathirana, V. Mihaila, A. Udrea, F. Amaratunga, G.A.J. Koutny, B. Ramkumar, K. Geha, S.
Copyright Year	2009
Description	Author affiliation: Cypress Semiconductor Corporation, San Jose, 198 Champion Ct., CA 95134, USA (Koutny, B.; Ramkumar, K.; Geha, S.) \|\| Cambridge Semiconductor Ltd - CamSemi, St Andrew's House, St Andrew's Road, CB4 1DL, UK (Trajkovic, T.; Udugampola, N.; Pathirana, V.; Mihaila, A.; Udrea, F.; Amaratunga, G.A.J.)
Abstract	A self-isolating, lateral IGBT device with high voltage blocking capability (≫700V), high on-state current density $(150A/cm^{2}$ at Vds=4V) and very fast turn-off (≪50ns), realized in membrane on bulk Si technology is reported here. The device has been manufactured using a standard 5V, 0.35µm bulk CMOS process on 8″ wafers with the addition of two masks: i) n-drift for the HV blocking region and ii) back-side Deep RIE (DRIE) for membrane formation. In comparison to PowerBrane on SOI, earlier reported by us [1,2], PowerBrane on bulk Si LIGBTs offer higher maximum power density due to better thermal dissipation and more robust operation including unclamped inductive switching and short circuit capability. Reliability of bulk-Si PowerBrane chips in plastic packages has been evaluated through HTRB tests and no failures have been observed after more than 1000 hours of stress. The DRIE step used for selective removal of portions of the silicon substrate, the key feature of PowerBrane technology, offers an effective solution for isolation of the high-voltage power LIGBT(s) from the control circuitry in monolithically integrated Power ICs. In addition, use of bulk Si wafers instead of more expensive SOI substrates reduces the manufacturing costs of PowerBrane-based Power ICs without compromising performance.
Starting Page	307
Ending Page	310
File Size	241606
Page Count	4
File Format	PDF
ISBN	9781424435258
ISSN	1943653X
DOI	10.1109/ISPSD.2009.5158063
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-14
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Frequency Biomembranes Power integrated circuits Insulated gate bipolar transistors Voltage Current density Manufacturing processes CMOS process Robustness
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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