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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Samsudin, K. Cheng, B. Brown, A.R. Roy, S. Asenov, A. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electron. & Electr. Eng., Glasgow Univ., UK (Samsudin, K.; Cheng, B.; Brown, A.R.; Roy, S.; Asenov, A.) |
| Abstract | Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra thin body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented. |
| Starting Page | 553 |
| Ending Page | 556 |
| File Size | 409389 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780392035 |
| DOI | 10.1109/ESSDER.2005.1546708 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-09-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Stability Fluctuations MOSFETs CMOS technology Electrostatics Immune system Circuit simulation Semiconductor process modeling Circuit noise |
| Content Type | Text |
| Resource Type | Article |
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