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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sun-Ghil Lee Young-Pil Kim Young-Eun Lee Jong-Wook Lee Insoo Jung Deok-Hyung Lee Yong-Hoon Son Sung-Kwan Kang Pilkyu Kang Min-Gu Kang Yu Gyun Shin U-In Chung Joo Tae Moon |
| Copyright Year | 2005 |
| Description | Author affiliation: Samsung Electron. Co., Ltd., Gyeonggi-Do, South Korea (Sun-Ghil Lee; Young-Pil Kim; Young-Eun Lee; Jong-Wook Lee; Insoo Jung; Deok-Hyung Lee; Yong-Hoon Son; Sung-Kwan Kang; Pilkyu Kang; Min-Gu Kang; Yu Gyun Shin; U-In Chung; Joo Tae Moon) |
| Abstract | We demonstrate a highly manufacturable substrate-induced strained Si device, which is compatible with the conventional Si bulk process. It utilizes ultra-thick-strained Si (UTSS) layer thicker than 3000 /spl Aring/ and relaxed SiGe layer with low Ge content less than 10%. The UTSS n-MOSFET gives 6 /spl sim/ 12% increase in I/sub on/ according to the gate length without the cost of increase in I/sub off/. In addition, more than 5% increase in I/sub on/ for p-MOSFET can be obtained by hybrid stress of UTSS and SiGe source/drain process. We also emphasize the importance of the ratio of channel resistance (R/sub CH/) to source-drain resistance (R/sub SD/) for performance enhancement. |
| Starting Page | 309 |
| Ending Page | 312 |
| File Size | 397922 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780392035 |
| DOI | 10.1109/ESSDER.2005.1546647 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-09-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon germanium Germanium silicon alloys Cascading style sheets MOSFET circuits Stress Costs Fabrication Moon Manufacturing processes Cleaning |
| Content Type | Text |
| Resource Type | Article |
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