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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hirairi, K. Okuma, Y. Fuketa, H. Yasufuku, T. Takamiya, M. Nomura, M. Shinohara, H. Sakurai, T. |
| Copyright Year | 2012 |
| Description | Author affiliation: University of Tokyo, Tokyo, Japan (Fuketa, H.; Yasufuku, T.; Takamiya, M.; Sakurai, T.) || Semiconductor Technology Academic Research Center, Tokyo, Japan (Hirairi, K.; Okuma, Y.; Nomura, M.; Shinohara, H.) |
| Abstract | Scaling power supply voltages (V's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V, adaptive V control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed. |
| Starting Page | 486 |
| Ending Page | 488 |
| File Size | 338085 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467303767 |
| ISSN | 01936530 |
| e-ISBN | 9781467303774 |
| DOI | 10.1109/ISSCC.2012.6177102 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-02-19 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Voltage control Temperature measurement Clocks Control systems Delay Adaptive systems |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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