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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dae Hyun Kim Athikulwongse, K. Healy, M. Hossain, M. Moongon Jung Khorosh, I. Kumar, G. Young-Joon Lee Lewis, D. Tzu-Wei Lin Chang Liu Panth, S. Pathak, M. Minzhen Ren Guanhao Shen Taigon Song Dong Hyuk Woo Xin Zhao Joungho Kim Ho Choi Loh, G. Hsien-Hsin Lee Sung Kyu Lim |
| Copyright Year | 2012 |
| Description | Author affiliation: Georgia Institute of Technology, Atlanta, GA (Dae Hyun Kim; Athikulwongse, K.; Healy, M.; Hossain, M.; Moongon Jung; Khorosh, I.; Kumar, G.; Young-Joon Lee; Lewis, D.; Tzu-Wei Lin; Chang Liu; Panth, S.; Pathak, M.; Minzhen Ren; Guanhao Shen; Taigon Song; Dong Hyuk Woo; Xin Zhao; Loh, G.; Hsien-Hsin Lee; Sung Kyu Lim) || Amkor Technology, Seoul, Korea (Ho Choi) || KAIST, Daejeon, Korea (Joungho Kim) |
| Abstract | Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in $5×5mm^{2}$ footprint. The chip runs at 1.5V and consumes up to 4W, resulting in $16W/cm^{2}$ power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM. |
| Starting Page | 188 |
| Ending Page | 190 |
| File Size | 271380 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467303767 |
| ISSN | 01936530 |
| e-ISBN | 9781467303774 |
| DOI | 10.1109/ISSCC.2012.6176969 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-02-19 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Three dimensional displays Through-silicon vias Timing Metals Random access memory Power demand Stacking |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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