NDLI: A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V-enhancing assist circuitry

Content Provider	IEEE Xplore Digital Library
Author	Karl, E. Yih Wang Yong-Gee Ng Zheng Guo Hamzaoglu, F. Bhattacharya, U. Zhang, K. Mistry, K. Bohr, M.
Copyright Year	2012
Description	Author affiliation: Intel, Hillsboro, OR (Karl, E.; Yih Wang; Yong-Gee Ng; Zheng Guo; Hamzaoglu, F.; Bhattacharya, U.; Zhang, K.; Mistry, K.; Bohr, M.)
Abstract	Future product applications demand increasing performance with reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM V and low-voltage performance as technology scaling follows Moore's law to the 22nm node. A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring $3^{rd}-generation$ high-k metal-gate transistors and $5^{th}-generation$ strained silicon. Tri-gate technology reduces short-channel effects (SCE) and improves subthreshold slope to provide 37% improved device performance at 0.7V. Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply drive current. Process-circuit co-optimization of transient voltage collapse write assist (TVC-WA) and wordline underdrive read assist (WLUD-RA) features address process variation and fin quantization at 22nm and enable a 175mV reduction in the supply voltage required for 2GHz SRAM operation. Figure 13.1.1 shows an SEM top-down view of a $0.092μm^{2}$ high-density 6T SRAM bitcell (HDC) and a $0.108μm^{2}$ low-voltage 6T SRAM cell (LVC) after gate and diffusion processing. Computational OPC/RET techniques extend the capabilities of 193nm immersion lithography to allow a 1.85× increase in array density relative to 32nm designs [1].
Starting Page	230
Ending Page	232
File Size	322829
Page Count	3
File Format	PDF
ISBN	9781467303767
ISSN	01936530
e-ISBN	9781467303774
DOI	10.1109/ISSCC.2012.6176988
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-02-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Arrays High K dielectric materials Silicon Performance evaluation Circuit stability CMOS integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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