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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tanabe, Y. Sumiyoshi, M. Nishiyama, M. Yamazaki, I. Fujii, S. Kimura, K. Aoyama, T. Banno, M. Hayashi, H. Miyamori, T. |
| Copyright Year | 2012 |
| Description | Author affiliation: Toshiba, Kawasaki, Japan (Tanabe, Y.; Sumiyoshi, M.; Nishiyama, M.; Yamazaki, I.; Fujii, S.; Kimura, K.; Aoyama, T.; Banno, M.; Hayashi, H.; Miyamori, T.) |
| Abstract | The use of image recognition technologies is becoming more popular recently in a variety of industries such as automotive, surveillance, and others. SoCs for such image recognition applications are required to be powerful enough to support real-time multiple object recognition, with power consumption not exceeding a few Watts. Adaptability to a range of applications is also desirable. In this context, massively parallel processors [1] and heterogeneous many-core processors [2] with 200GOPS have been proposed. However, rising demands for simultaneous execution of multiple applications leads to even higher performance requirements. In advanced driver-assistance systems for automotive, for example, forward collision warning and traffic sign recognition should execute simultaneously to improve safety of the system. In addition, the accuracy of recognition is also important. With its high accuracy (96% detection rate/0.1% false-positive rate), object recognition using co-occurrence histograms of oriented gradients (CoHOG) is a promising algorithm [3]. However, the algorithm requires an extensive amount of computation. For example, a desktop computer with a 3GHz quad-core processor is needed for CoHOG-based pedestrian detection in a backover prevention (BOP) application. Considering these requirements, we have developed an image recognition SoC with the following features: 1) a multi-core processor to provide adaptability to various applications; 2) accelerators for image processing tasks and image recognition tasks to realize high performance at low power consumption; and, 3) a hardware accelerator for a CoHOG based real-time recognition. |
| Starting Page | 222 |
| Ending Page | 223 |
| File Size | 311086 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781467303767 |
| ISSN | 01936530 |
| e-ISBN | 9781467303774 |
| DOI | 10.1109/ISSCC.2012.6176984 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-02-19 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Program processors System-on-a-chip Image recognition Multicore processing Power demand Parallel processing Histograms |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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