NDLI: Digital LDO with 1-bit ΔΣ modulation for low-voltage clock generation systems

Content Provider	IET Digital Library
Author	Song, Haixin Rhee, Woogeun Shim, Inbo Wang, Zhihua
Abstract	A coarse-fine dual-loop digital low dropout regulator (DLDO) having a binary weighed transistor array in the coarse loop and a 1-bit ΔΣ modulator in the fine loop is proposed. Compared with the conventional DLDO, the proposed architecture significantly reduces hardware complexity and alleviates matching requirement, enabling a robust DLDO design for low-voltage phase-locked loops. The proposed DLDO designed in 65 nm CMOS generates a noise-shaped output voltage whose peak value is <1 mV with the load current ranging from 100 μA to 6 mA.
Starting Page	2034
Ending Page	2036
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 25, Dec (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/25
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.2982
Journal	Electronics Letters
Publisher Date	2016-11-15
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Binary Weighed Transistor Array Clocks CMOS Digital Integrated Circuit CMOS Integrated Circuit CMOS Process Coarse-fine Dual-loop Digital Low Dropout Regulator Current 100 MuA to 6 MA Delta-sigma Modulation Digital LDO Hardware Complexity Reduction Low-voltage Clock Generation System Low-voltage Phase-locked Loops Noise-shaped Output Voltage Phase Locked Loop Power Electronics Power Supply Robust DLDO Design Size 65 Nm Supervisory Circuit Voltage Regulators Word Length 1 Bit ΔΣ Modulation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Digital LDO regulator with analogue-assisted loop using source follower

Flash ADC-based digital LDO with non-linear decoder and exponential-ratio array

Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

Power-area-efficient transient-improved capacitor-free FVF-LDO with digital detecting technique

Ultralow-power fast-transient output-capacitor-less low-dropout regulator with advanced adaptive biasing circuit

All-digital PLL with ΔΣ DLL embedded TDC

Fast-transient high-performance 0.18 μm CMOS LDO for battery-powered systems

Low-power, wide-range time-to-digital converter for all digital phase-locked loops

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Digital LDO with 1-bit ΔΣ modulation for low-voltage clock generation systems

Similar Documents

Digital LDO regulator with analogue-assisted loop using source follower

Flash ADC-based digital LDO with non-linear decoder and exponential-ratio array

Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

Power-area-efficient transient-improved capacitor-free FVF-LDO with digital detecting technique

Ultralow-power fast-transient output-capacitor-less low-dropout regulator with advanced adaptive biasing circuit

All-digital PLL with ΔΣ DLL embedded TDC

Fast-transient high-performance 0.18 μm CMOS LDO for battery-powered systems

Low-power, wide-range time-to-digital converter for all digital phase-locked loops

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Digital LDO with 1-bit ΔΣ modulation for low-voltage clock generation systems