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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tochigi, Y. Hanzawa, K. Kato, Y. Kuroda, R. Mutoh, H. Hirose, R. Tominaga, H. Takubo, K. Kondo, Y. Sugawa, S. |
| Copyright Year | 2012 |
| Description | Author affiliation: Shimadzu, Kyoto, Japan (Hirose, R.; Tominaga, H.; Takubo, K.; Kondo, Y.) || Link Research, Odawara, Japan (Mutoh, H.) || Tohoku University, Sendai, Japan (Tochigi, Y.; Hanzawa, K.; Kato, Y.; Kuroda, R.; Sugawa, S.) |
| Abstract | Researchers in many advanced R&D and scientific instrumentation fields must analyze high-speed phenomena through the use of high-speed video cameras with over 1Mfps. Conventional image sensors are mainly rolling-shutter continuous CMOS image sensors that repeat exposure and read-out signals quickly for every frame [1]. A global shutter is a necessity in this field because objects move very fast. Recently, global shutter CMOS image sensors with column-parallel ADCs [2] or analog parallel-output circuits [3] have been reported. A higher frame rate can be achieved by reducing the number of pixels. Consequently, the read-out speed, namely the frame rate times the number of pixels, is limited at around 10Gpixel/s in the conventional global-shutter CMOS image sensors. To improve the read-out speed, global-shutter burst CCD image sensors with multiple storage CCD memories for storing image signals near the photodiode in each pixel have been reported [4]. The image sensor in [4] achieves 1Tpixel/s; however it has issues such as high heat generation due to driving large CCD capacitors simultaneously, an inability to achieve continuous operation, and a decrease of charge capacity at near-maximum frame rates. A prototype global-shutter CMOS image sensor that has multiple on-chip memories is reported in [5]. This sensor achieves both 23Gpixel/s burst operation without cooling and 23Mpixel/s continuous operation on a single chip. This paper presents a $400^{H}×256^{V}$ pixel CMOS image sensor including 128 on-chip memory/pixel with 1Tpixel/s in burst operation without cooling and 780Mpixel/s in continuous operation. To improve the read-out speed from the chip, a noise-reduction circuit in pixel and relay buffers is introduced. |
| Starting Page | 382 |
| Ending Page | 384 |
| File Size | 368982 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467303767 |
| ISSN | 01936530 |
| e-ISBN | 9781467303774 |
| DOI | 10.1109/ISSCC.2012.6177046 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-02-19 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analog memory CMOS image sensors Capacitors Switching circuits Noise Timing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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