NDLI: A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS

Content Provider	IEEE Xplore Digital Library
Author	Li, Y.W. Ornelas, C. Hyung Seok Kim Lakdawala, H. Ravi, A. Soumyanath, K.
Copyright Year	2012
Description	Author affiliation: Intel, Guadalajara, Mexico (Ornelas, C.) \|\| Intel, Hillsboro, OR (Li, Y.W.; Hyung Seok Kim; Lakdawala, H.; Ravi, A.; Soumyanath, K.)
Abstract	As platform integration continues, different modules, including CPU, graphics, I/O interface, wireless transceivers and the power management unit, operate at different frequencies as shown in Fig. 3.8.1. In addition, maximizing battery life requires localized dynamic voltage frequency scaling (DVFS) and sleep mode support leading to independent clock domains for various functional unit blocks (FUBs). Also, clock generation units should be able to go to sleep and wake up rapidly to conserve power. Generating multiple clock signals while minimizing skews at the module interfaces is challenging. Furthermore, some modules require spread spectrum clocking (SSC), with different modulation patterns to avoid EMI, but yet such spreading is forbidden in modules requiring frequency accuracy (e.g. display interfaces). Diverse SSC generation requirements necessitate multiple reference clocks, extra pins, and off-chip components. With analog integer-n PLL-based clock generators, it is difficult to meet all these needs with a common reference clock. One disadvantage is that the frequency resolution in an integer-n PLL is limited by the reference frequency. A lower reference frequency limits the bandwidth and lock time, amplifies jitter from the reference, and increases the loop filter area. Additionally, analog PLLs suffer from unpredictable loop dynamics and clock skews with PVT, mismatch, and transistor leakage, further exacerbated by process scaling. Turning off and waking up an analog PLL requires charging or discharging loop filter capacitors which is inherently slow. This paper presents an all-digital clock generation architecture which (1) provides fractional-n capability in the digital domain; (2) implements SSC within the PLL loop; (3) performs digital clock deskew; and (4) provides dynamic loop bandwidth adjustment to shorten lock time.
Starting Page	70
Ending Page	72
File Size	313399
Page Count	3
File Format	PDF
ISBN	9781467303767
ISSN	01936530
e-ISBN	9781467303774
DOI	10.1109/ISSCC.2012.6176934
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-02-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Phase locked loops Frequency modulation Voltage-controlled oscillators Jitter Computer architecture
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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