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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Won-ok Kwon Hyuk-je Kwon Kyoung Park |
| Copyright Year | 2004 |
| Description | Author affiliation: Digital Home Dept., Electron. & Telecommun. Res. Inst., Deajeon, South Korea (Won-ok Kwon) |
| Abstract | Removing lane-to-lane skew is a very important function in a multi-channel receiver using high-speed serial protocols. This paper deals with implementation of data skew removing logic for the PCI Express protocol. We proposes 16 bit multi-lane de-skew logic to satisfy the PCI Express protocol specifications. This logic is optimized for general-purpose FPGA design. The proposed logic is verified by RTL simulation and implemented in an FPGA embedded programmable SERDES. The measured results agree well with the simulation results. |
| Starting Page | 2035 |
| Ending Page | 2038 |
| File Size | 1225750 |
| Page Count | 4 |
| File Format | |
| ISBN | 078038511X |
| DOI | 10.1109/ICSICT.2004.1435242 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-10-18 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic design Field programmable gate arrays Physical layer Protocols Clocks Logic devices Computational modeling Computer architecture Personal communication networks Consumer electronics |
| Content Type | Text |
| Resource Type | Article |
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