NDLI: A novel methodology for Multi-Project System-on-a-Chip

Content Provider	IEEE Xplore Digital Library
Author	Chih-Chyau Yang Nien-Hsiang Chang Shih-Lun Chen Wei-De Chien Chi-Shi Chen Chien-Ming Wu Chun-Ming Huang
Copyright Year	2011
Description	Author affiliation: National Chip Implementation Center (CIC), Hsinchu, Taiwan (Chih-Chyau Yang; Nien-Hsiang Chang; Shih-Lun Chen; Wei-De Chien; Chi-Shi Chen; Chien-Ming Wu; Chun-Ming Huang)
Abstract	In this paper, a novel silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. For integrating heterogeneous SoC projects into a single chip, the current SoC methodology is insufficient due to the complexity of MP-SoC. In order to improve the robustness of MP-SoC design and verification, a new design flow was developed. It consists of a virtual platform, a logical implementation, a rapid prototyping platform, a physical implementation, and testing stages. The virtual platform is a system modeling and hardware/software co-design system by using electronic system level (ESL). VIP system is adopted for the AMBA-compliant check of the interfaces of the MP-SoC. In addition, STEAC and DFT were used to facilitate MP-SoC testing integration. The rapid prototyping platform called “CONCORD” which has characteristics of connection flexibility, modularization, and consistence architecture for emulating the hardware of MP-SoC before chip being taped out. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoC projects sharing the common platform. The total silicon area is about $37.97mm^{2}$ in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area $129.39mm^{2}$ by implementing these projects separately, the results show that there are 91.42 $mm^{2}$ or 70.6 % silicon area reduced by this novel silicon prototyping methodology.
Starting Page	308
Ending Page	311
File Size	1249826
Page Count	4
File Format	PDF
ISBN	9781457716164
ISSN	21641706
e-ISBN	9781457716171
e-ISBN	9781457716157
DOI	10.1109/SOCC.2011.6085090
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Silicon IP networks Hardware Testing Educational institutions Computer architecture CONCORD Multi-Project SoC Silicon Prototyping
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A configurable prototyping platform for multi-project system-on-a-chip

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Programmable System-on-Chip for Silicon Prototyping

A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping

Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software

Programmable System-on-Chip (SoC) for silicon prototyping

A prototyping IP for mobile computing SOC

PrSoC: Programmable System-on-chip (SoC) for silicon prototyping

The reconfigurable IP modules and design

A novel methodology for Multi-Project System-on-a-Chip

Similar Documents

A configurable prototyping platform for multi-project system-on-a-chip

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Programmable System-on-Chip for Silicon Prototyping

A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping

Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software

Programmable System-on-Chip (SoC) for silicon prototyping

A prototyping IP for mobile computing SOC

PrSoC: Programmable System-on-chip (SoC) for silicon prototyping

The reconfigurable IP modules and design

A novel methodology for Multi-Project System-on-a-Chip