NDLI: De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips

Content Provider	IEEE Xplore Digital Library
Author	Sanusi, A. Bayoumi, M.A.
Copyright Year	2011
Description	Author affiliation: The Center for Advance Computer Studies, The University of Louisiana at Lafayette, USA (Sanusi, A.; Bayoumi, M.A.)
Abstract	Multi-level caches are used in multiprocessor systems to exploit locality of data and decrease the bandwidth demands on the network. Apart from exploiting locality in large-scale networks, we must also amortize the cost of distant communication so as to reduce memory request latency which is a critical determinant of multiprocessor performance. Our proposed architecture called the De-Cache ($De) architecture exploits the nature of the network-on-chip (NoC) structure by introducing what we called detour caches to store data from the most distant physical memory locations closer to the requesting node. Our experiments show that by using our proposed $De architecture we can decrease the memory request latency up to approximately 29.0% with very little degradation to the network performance.
Starting Page	191
Ending Page	196
File Size	882820
Page Count	6
File Format	PDF
ISBN	9781457716164
ISSN	21641706
e-ISBN	9781457716171
e-ISBN	9781457716157
DOI	10.1109/SOCC.2011.6085079
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Approximation methods Table lookup
Content Type	Text
Resource Type	Article

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