NDLI: A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow

Content Provider	IEEE Xplore Digital Library
Author	Salem, R.F. Arafa, A. Hany, S. ElMously, A. Eissa, H. Dessouky, M. Nairn, D. Anis, M.H.
Copyright Year	2011
Description	Author affiliation: University of Waterloo, Canada (Nairn, D.) \|\| Mentor Graphics Corporation, USA (Salem, R.F.; Arafa, A.; Hany, S.; ElMously, A.; Eissa, H.; Dessouky, M.) \|\| The American University in Cairo, Egypt (Anis, M.H.)
Abstract	As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has been an increased emphasis on parametric yield issues, referred to as electrical-DFM (e-DFM). In this paper, we present a complete electrical-aware design for manufacturing solution that detects, analyzes, and fixes electrical hotspots (e-hotspots) caused by different process variations within the analog circuit design. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 65nm industrial voltage control oscillator (VCO). E-hotspot devices with 5.5% variation in DC current are identified. After fixing the e-hotspots, the DC current variation in these devices is reduced to 0.9%, while saving the original VCO specifications.
Starting Page	231
Ending Page	236
File Size	1111245
Page Count	6
File Format	PDF
ISBN	9781457716164
ISSN	21641706
e-ISBN	9781457716171
e-ISBN	9781457716157
DOI	10.1109/SOCC.2011.6085082
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Layout Engines Stress SPICE Voltage-controlled oscillators Lithography e-hotspot Process variations Design-For-Manufacturability design for manufacturing DFM Lithography variations Stress effects Electrical Design For Manufacturability electrical design for manufacturing e-DFM Parametric Yield
Content Type	Text
Resource Type	Article

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