NDLI: Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers

Content Provider	IEEE Xplore Digital Library
Author	Chakraborty, A. Duraisami, K. Sathanur, A. Sithambaram, P. Benini, L. Macii, A. Macii, E. Poncino, M.
Copyright Year	2006
Description	Author affiliation: Politecnico di Torino (Chakraborty, A.; Duraisami, K.; Sathanur, A.; Sithambaram, P.)
Abstract	The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, re-design of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this work, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed off-line and, stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with minimum area and power penalty. The maximum increase in power is 23.2% with most benchmarks exhibiting less than 5% increase in power
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	162
Ending Page	167
File Size	3073131
Page Count	6
File Format	PDF
ISBN	1595934626
DOI	10.1109/LPE.2006.4271829
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-04
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Delay Tunable circuits and devices Temperature sensors Integrated circuit interconnections Temperature distribution Power dissipation Energy management Thermal management Buffer storage temperature aware design methodology Algorithms designi performance Clock tree clock skew tunable delay buffers
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

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