NDLI: Process Variation Aware Cache Leakage Management

Content Provider	IEEE Xplore Digital Library
Author	Ke Meng Joseph, R.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL (Ke Meng; Joseph, R.)
Abstract	In a few technology generations, limitations of fabrication processes have made accurate design time power estimates a daunting challenge. Static leakage current which comprises a significant fraction of total power due to large on-chip caches, is exponentially dependent on widely varying physical parameters such as gate length, gate oxide thickness, and dopant ion concentration. In large structures like on-chip caches, this may mean that one portion of a cache may consume an order of magnitude larger static power than equivalently sized regions. Under this climate, egalitarian management of physical resources is clearly untenable. In this paper, we analyze the effects of within-die and die-to-die leakage variation for on-chip caches. We then propose way prioritization, a manufacturing variation aware scheme that minimizes cache leakage energy. Our results show that significant average power reductions are possible without undue hardware complexity or performance compromise
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	262
Ending Page	267
File Size	3025795
Page Count	6
File Format	PDF
ISBN	1595934626
DOI	10.1109/LPE.2006.4271847
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-04
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Manufacturing Hardware Power generation Fabrication Permission Circuits Cache memory Engineering management Resource management Memory management selective cache ways Design Performance Experimentation process variation low power leakage cache management Gated-VDD
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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