NDLI: Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers

Content Provider	IEEE Xplore Digital Library
Author	Ragheb, T. Ricketts, A. Mondal, M. Kirolos, S. Links, G.M. Narayanan, V. Massoud, Y.
Copyright Year	2004
Abstract	On-chip temperature gradient has emerged as a major design concern for high-performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. The main aim of this paper is to provide intelligent solution for minimizing the temperature-dependent clock skew by designing dynamically adaptive circuit elements, particularly the clock buffers. Using an RLC model of the clock tree, we investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles that can arise in practice due to different architectures and applications. As an effective way of mitigating the variable clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by up to 92.4%, leading to much improved clock synchronization and design performance.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	374
Ending Page	383
Page Count	10
File Size	1209135
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Robustness Temperature sensors Integrated circuit interconnections RLC circuits Aluminum Threshold voltage Integrated circuit technology Digital circuits Circuit simulation temperature sensor Adaptive clock buffers clock skew clock tree temperature gradient
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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