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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Elham Safi Moshovos, A. Veneris, A. |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Toronto Univ., Ont. (Elham Safi; Moshovos, A.; Veneris, A.) |
| Abstract | We study the energy, latency and area characteristics of two counting bloom filter implementations using full custom layouts in a commercial 0.13mum technology. The first implementation, S-CBF, uses an SRAM array of counts and a shared counter. The second, L-CBF, utilizes an array of up/down linear feedback shift registers. Circuit level simulations demonstrate that for a 1K-entry CBF with a 15-bit count per entry, L-CBF is 3.7 or 1.6 times faster than the S-CBF depending on the operation. The L-CBF requires 2.3 or 1.4 times less energy per operation compared to the S-CBF. However, the L-CBF requires 3.2 times more area. We demonstrate that for one application of CBFs (early hit/miss detection for L1 caches (Peir, 2002) for an aggressive dynamically-scheduled superscalar processor) the energy consumed by the L-CBF is 60% of the energy consumed by the S-CBF for most of the SPEC CPU 2000 benchmarks |
| Sponsorship | ACM SIGDA IEEE Circuits and Syst. Soc |
| Starting Page | 250 |
| Ending Page | 255 |
| File Size | 1984765 |
| Page Count | 6 |
| File Format | |
| ISBN | 1595934626 |
| DOI | 10.1109/LPE.2006.4271845 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-10-04 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Filters Delay Testing Linear feedback shift registers Hardware CMOS technology Computer architecture Power engineering and energy Random access memory Counting circuits Energy per Operation Design Measurement Performance Experimentation Counting Bloom Filters Processors |
| Content Type | Text |
| Resource Type | Article |
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