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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hyunseok Lee Mudge, T. Chakrabarti, C. |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of EECS, Michigan Univ., Ann Arbor, MI (Hyunseok Lee; Mudge, T.) |
| Abstract | In this paper, we propose a processor which is optimized for idle mode operation of a software defined radio (SDR) terminal. Since a SDR terminal spends most of its time in the idle mode, reducing the power consumption in this mode directly translates to longer terminal standby time. Workload analysis of idle mode operations of contemporary standards showed that these are dominated by FIR filtering, which can be easily parallelized. This analysis was used in the design of the idle mode processor. The key architectural components are an SIMD unit for the parallel computations that dominate the workload, a conventional scalar unit for the sequential computations, and a control unit which supports efficient data memory access and loop control. The idle mode processor was modeled with Verilog and synthesized using standard cells in 0.13 micron technology. It consumes about 9mW at 1.08V |
| Sponsorship | ACM SIGDA IEEE Circuits and Syst. Soc |
| Starting Page | 101 |
| Ending Page | 106 |
| File Size | 2263203 |
| Page Count | 6 |
| File Format | |
| ISBN | 1595934626 |
| DOI | 10.1109/LPE.2006.4271815 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-10-04 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Software radio Baseband Finite impulse response filter Wireless communication Signal processing algorithms Energy consumption Filtering Concurrent computing Computer architecture Hardware SIMD Design Performance Software defined radio SDR Wireless terminal Baseband processor Idle mode Low power |
| Content Type | Text |
| Resource Type | Article |
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