NDLI: A 66.1 Gbps single-pipeline AES on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Qiang Liu Zhenyu Xu Ye Yuan
Copyright Year	2013
Description	Author affiliation: Sch. of Electron. Inf. Eng., Tianjin Univ., Tianjin, China (Qiang Liu; Zhenyu Xu; Ye Yuan)
Abstract	Targeting real-time encryption/decryption of high speed data communication, this paper proposes an FPGA-based high throughput AES design. The critical functions involved in AES are broken into elementary logic operations to gain the deep insight into the performance bottleneck. With respect to FPGA structures, a datapath with two balanced pipeline stages is determined for each of the encryption/decryption rounds. Meanwhile, a new key expansion scheme with additional nonlinear operations is proposed to increase the security of the AES implementation and is well matched to the two-stage pipelining datapath. The design is evaluated on various FPGA devices and is compared with several existing AES implementations. Results show that in terms of both throughput and throughput per slice the proposed AES design with single pipeline can overcome most existing designs and achieves a throughput of 66.1 Gbps on a latest FPGA device.
Starting Page	378
Ending Page	381
File Size	253737
Page Count	4
File Format	PDF
e-ISBN	9781479921980
DOI	10.1109/FPT.2013.6718392
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Throughput Pipeline processing Table lookup Delays Encryption Routing
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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