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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gorman, C. Siqueira, P. Tessier, R. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA (Gorman, C.; Siqueira, P.; Tessier, R.) |
| Abstract | In this demonstration, we present an open-source Serial ATA core designed for Virtex-4 FPGAs. This core utilizes the RocketIO Multi-Gigabit Transceiver (MGT) of the Virtex-4 to interface with hard drives at SATA Generation 1 (SATA I, 1.5 Gb/s) and Generation 2 (SATA II, 3.0 Gb/s) speeds. A full design hierarchy from host software to the physical layer is provided with the distribution to facilitate design use. A simple, FIFO interface allows for easy integration with other FPGA modules. The demonstration illustrates the correct write and read behavior of the core using a Xilinx ML405 board and a solid state disk. The peak transfer rate of the core for SATA I (130 MB/s) is demonstrated. Our goal for the demonstration is to educate the reconfigurable computing community regarding the availability of the core and to illustrate its capabilities. |
| Starting Page | 454 |
| Ending Page | 457 |
| File Size | 646506 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781479921980 |
| DOI | 10.1109/FPT.2013.6718413 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-09 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Clocks Open source software Physical layer Protocols Transceivers Debugging |
| Content Type | Text |
| Resource Type | Article |
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