NDLI: On a High-Performance and Balanced Method of Hardware Implementation for AES

Content Provider	IEEE Xplore Digital Library
Author	Xiaotao Zhang Hui Li Shouwen Yang Shuangshuang Han
Copyright Year	2013
Description	Author affiliation: Univ. of Maryland, College Park, MD, USA (Shuangshuang Han) \|\| Inf. Security & Intell. Comput. Lab., Beijing Univ. of Chem. Technol., Beijing, China (Xiaotao Zhang; Hui Li; Shouwen Yang)
Abstract	Hardware implementation provides a higher level of security and cryptography speed at some lower resource cost, compared to software implementation of AES. In this paper, we present a balanced hardware design and implementation for AES, considering several existing implementations. FPGA implementation offers higher speed solution and can be easily adapted to protocol changes, although the AES can be implemented with software or pure hardware. So, this implementation is equipped with regard to FPGA. Optimized and Synthesizable Verilog HDL is developed as the design entry to Quartus II 10.0 software. After obtaining gate-level netlists, timing simulations are performed using ModelSim SE 6.1f. Both 128 bits data block encryption and decryption processes are tested. The major part of an AES design is the realization of substitute boxes (S-boxes). S-boxes in our design are compared between two main existing implementations. With Quartus II device family of Stratix, throughput of up to 2.33 Gb/s is received.
Starting Page	16
Ending Page	20
File Size	2377899
Page Count	5
File Format	PDF
e-ISBN	9781479929252
DOI	10.1109/SERE-C.2013.13
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Ciphers Balanced Hardware Implementation Rijndael FPGA Throughput Hardware Encryption Table lookup Field programmable gate arrays AES
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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