NDLI: An automated flow for the High Level Synthesis of coarse grained parallel applications

Content Provider	IEEE Xplore Digital Library
Author	Castellana, V.G. Ferrandi, F.
Copyright Year	2013
Description	Author affiliation: Politec. di Milano, DEIB, Milan, Italy (Castellana, V.G.; Ferrandi, F.)
Abstract	High Level Synthesis (HLS) provides a way to significantly enhance the productivity of embedded system designers, by enabling the automatic or semiautomatic generation of hardware accelerators starting from high level descriptions with (usually software) programming languages. Typical HLS approaches build a centralized Finite State Machine (FSM) to control the generated datapath, performing the operations according to a pre-determined, static schedule. However, FSM-based approaches are only able to extract parallelism within a single execution flow. In the presence of coarse grained parallelism, in the form of concurrent function calls or parallel control structures, they either serialize all the operations, or build excessively complex controllers, aiming at executing as many operation as possible in a single control step (i.e., they try to extract as much instruction level parallelism as possible). The resulting controllers occupy an excessive amount of area or lead to very low operating frequencies. In this paper we propose a methodology for the HLS of accelerators supporting parallel execution and dynamic scheduling. The approach exploits an adaptive distributed controller, composed of a set of communicating elements associated with each operation. This controller design enables supporting multiple concurrent execution flows, thus increasing parallelism exploitation beyond instruction level parallelism. The approach also supports variable latency operations, such as memory accesses and speculative operations. We apply our methodology on a set of typical HLS benchmarks, and demonstrate valuable speed ups with limited area overheads with respect to conventional FSM-based flows.
Starting Page	294
Ending Page	301
File Size	566782
Page Count	8
File Format	PDF
e-ISBN	9781479921980
DOI	10.1109/FPT.2013.6718370
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Dynamic scheduling Processor scheduling Complexity theory Runtime Hardware
Content Type	Text
Resource Type	Article

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