NDLI: Multi-personality partitioning for heterogeneous systems

Content Provider	IEEE Xplore Digital Library
Author	Gregerson, A. Chadha, A. Morrow, K.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Wisconsin - Madison, Madison, WI, USA (Gregerson, A.; Chadha, A.; Morrow, K.)
Abstract	Design flows use graph partitioning both as a precursor to place and route for single devices, and to divide netlists or task graphs among multiple devices. Partitioners have accommodated FPGA heterogeneity via multi-resource constraints, but have not yet exploited the corresponding ability to implement some computations in multiple ways (e.g., LUTs vs. DSP blocks), which could enable a superior solution. This paper introduces multi-personality graph partitioning, which incorporates aspects of resource mapping into partitioning. We present a modified multi-level KLFM partitioning algorithm that also performs heterogeneous resource mapping for nodes with multiple potential implementations (multiple personalities). We evaluate several variants of our multi-personality FPGA circuit partitioner using 21 circuits and benchmark graphs, and show that dynamic resource mapping improves cut size on average by 27% over static mapping for these circuits. We further show that it improves deviation from target resource utilizations by 50% over post-partitioning resource mapping.
Starting Page	314
Ending Page	317
File Size	5975215
Page Count	4
File Format	PDF
e-ISBN	9781479921980
DOI	10.1109/FPT.2013.6718375
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Partitioning algorithms Field programmable gate arrays Benchmark testing Heuristic algorithms Resource management Dynamic scheduling Digital signal processing technology mapping partitioning
Content Type	Text
Resource Type	Article

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