NDLI: The architecture and placement algorithm for a uni-directional routing based 3D FPGA

Content Provider	IEEE Xplore Digital Library
Author	Junsong Hou Heng Yu Yajun Ha Xin Liu
Copyright Year	2013
Description	Author affiliation: Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore (Xin Liu) \|\| Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore (Junsong Hou; Heng Yu; Yajun Ha)
Abstract	Three-Dimensional (3D) FPGA as a promising design trend, achieves significant performance improvement over conventional 2D-based FPGA. The maturity of the uni-directional routing architecture design, which achieves 25% area saving in area-delay-product (ADP) over bi-directional routing architectures, has driven major vendors such as Xilinx and Altera to switch to such architecture in their 2D-based products. However, few studies were contributed to exploring performance-optimal uni-directional 3D routing architectures. In this paper, we propose and evaluate a novel uni-directional 3D routing architecture named UNI-3D. Additionally, in the EDA counterpart, we also propose an improved simulated annealing (SA)-based placement algorithm that caters the unidirectional architecture, to alleviate signal propagation imbalance in the vertical channels resulted from using conventional bi-directional based SA approach. Our simulation results show that our proposed architecture is able to achieve up to 28.44% of delay reduction and 26.21% planar channel width reduction compared with the baseline 2D uni-directional architecture. At the same time, the proposed SA algorithm is able to improve the average vertical channel width up to 16% compared to state-of-the-art works.
Starting Page	28
Ending Page	33
File Size	1218019
Page Count	6
File Format	PDF
e-ISBN	9781479921980
DOI	10.1109/FPT.2013.6718325
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Three-dimensional displays Routing Field programmable gate arrays Through-silicon vias Multiplexing Delays
Content Type	Text
Resource Type	Article

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