NDLI: Accelerating on-line training of LS-SVM with run-time reconfiguration

Content Provider	IEEE Xplore Digital Library
Author	Shaojun Wang Yu Peng Guangquan Zhao Xiyuan Peng
Copyright Year	2011
Description	Author affiliation: School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin, China (Shaojun Wang; Yu Peng; Guangquan Zhao; Xiyuan Peng)
Abstract	Least Squares Support Vector Machines(LS-SVM), which is an efficient supervised learning tool, has been widely applied to real-time on-line data processing in many fields. However, the on-line training of LS-SVM always suffers from huge computation which greatly limits its practicability especially in embedded systems. By leveraging the flexibility and high degree parallelism offered by reconfigurable fabrics, we propose a Run-Time Reconfiguration(RTR) framework to accelerate the on-line training of LS-SVM. To realize maximum computational parallelism, we divide the training process into two parts, the kernel matrix formulation and the least-square problem solving. We dynamically load these two parts into FPGA with RTR under the control of the embedded PowerPC. In the kernel matrix formulation part, we design a piecewise linear interpolation method to realize the radial basis function. In the least-square problem solving part, the modified Cholesky Decomposition is introduced to avoid the latency caused by square roots operations. The whole design is tested on Virtex XC5VFX130T with a 150MHz clock. The experiments show appealing speed up which ranges from 6∼218× over a Xeon CPU implementation on five different sized datasets. From time cost percentage analysis, our proposed architecture can be effectively applied to LS-SVM training in more than 1000 samples applications.
Starting Page	1
Ending Page	6
File Size	474968
Page Count	6
File Format	PDF
ISBN	9781457717413
e-ISBN	9781457717406
DOI	10.1109/FPT.2011.6132697
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-12
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Kernel Training Random access memory Computer architecture Field programmable gate arrays Matrix decomposition Hardware Custom Computing Run Time Reconfiguration LS-SVM FPGA
Content Type	Text
Resource Type	Article

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