NDLI: VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration

Content Provider	IEEE Xplore Digital Library
Author	Kapre, N. DeHon, A.
Copyright Year	2011
Description	Author affiliation: Imperial College London, London, SW7 2AZ (Kapre, N.) \|\| University of Pennsylvania, Philadelphia, PA 19104 (DeHon, A.)
Abstract	Many stand-alone, FPGA-based accelerators separate the implementation of a computation into two components — (1) a large parallel component that is realized as hardware on spatial FPGA fabric and (2) a small control and co-ordination component that is realized as software on embedded soft-core processors like an off-the-shelf Xilinx Microblaze (or host offchip CPU). While this hardware-software partitioning methodology allows the designer to lower design effort when composing the accelerator system, it introduces unnecessary Amdahl's Law bottlenecks and limits scalability. In this paper, we show how to avoid these limitations with VLIW-SCORE: a combination of a high-level parallel programming framework called SCORE and a custom, hybrid VLIW hardware organization. We demonstrate the benefits of this methodology for the SPICE circuit simulator when implementing the simulation control algorithms. With our spatial mapping flow we are able to improve performance by ≈30% (mean across circuit benchmarks) when compared to the Microblaze implementation for the Xilinx Virtex-6 LX760 FPGA. For complete application acceleration, we see an improved speedup from 1.9× for the Microblaze-based design to 2.6× for the hybrid, custom VLIW implementation when comparing a Xilinx Virtex-6 LX760 FPGA (40nm) with an Intel Core i7 965 CPU (45nm).
Starting Page	1
Ending Page	9
File Size	515395
Page Count	9
File Format	PDF
ISBN	9781457717413
e-ISBN	9781457717406
DOI	10.1109/FPT.2011.6132678
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-12
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SPICE Field programmable gate arrays VLIW Mathematical model Computer architecture Computational modeling Runtime
Content Type	Text
Resource Type	Article

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