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2015 International Conference on Field Programmable Technology (FPT)

2013 International Conference on Field-Programmable Technology (FPT)

2012 International Conference on Field-Programmable Technology

2011 International Conference on Field-Programmable Technology

Message from the general chairs

Message from the program chairs

Message from the design competition chairs

FPT 2011 committee members

Field-programmable technology: The next ten years and beyond

Value of rapid prototyping in building complex digital systems

Building Root of Trust

Reconfigurable acceleration and dynamic partial self-reconfiguration in general purpose computing

A framework for FPGA acceleration of large graph problems: Graphlet counting case study

Cool Mega-Array: A highly energy efficient reconfigurable accelerator

A self-healing autonomous neural network hardware for trustworthy biomedical systems

FPGA implementation of reconfigurable ADPLL network for distributed clock generation

A framework for verifying functional correctness in Odin II

Floating-point mixed-radix FFT core generation for FPGA and comparison with GPU and CPU

An analysis of ring oscillator PUF behavior on FPGAs

A low power technology mapping method for Adaptive Logic Module

Hydrate: Hybrid Reconfigurable Architecture Expressions

A novel architecture for a secure update of cryptographic engines on trusted platform module

Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture

VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration

Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm

Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates

Variable and clause elimination in SAT problems using an FPGA

Constant power reconfigurable computing

An analytical energy model to accelerate FPGA logic architecture investigation

Accelerated FPGA architecture design: Capabilities and limitations of analytical models

A scalable memory interface for multicore reconfigurable computing systems

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator

3D implication logic: Preliminary results

Enabling high level design of adaptive systems with partial reconfiguration

Architecture and tools for programmable QCA

A unified emulation/simulation environment for reconfigurable system-on-chip development

Exploring FPGA technology mapping for fracturable LUT minimization

Automating formal verification of customized soft-processors

Operational mode exploration for reconfigurable systems with multiple applications

FPGA power consumption measurements and estimations under different implementation parameters

Objective-driven workload allocation in heterogeneous computing systems

Design methodology for FPGA implementation of lattice piecewise-affine functions

Accelerating on-line training of LS-SVM with run-time reconfiguration

High speed low complexity FPGA-based FIR filters using pipelined adder graphs

Formulation-level design space exploration for partially reconfigurable FPGAs

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Spiking neural network-based auto-associative memory using FPGA interconnect delays

A reconfigurable macro-pipelined systolic accelerator architecture

Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips

Investigation of NBTI and PBTI induced aging in different LUT implementations

A novel architecture for a secure update of cryptographic engines on trusted platform module

Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Partially reconfigurable system-on-chips for adaptive fault tolerance

ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration

Hardware-accelerated execution of Pi-calculus reconfiguration schedules

Design & development of soft-core processor based remote terminal units for nuclear reactors

A scalable network port scan detection system on FPGA

An adaptive-method for velocity estimation using time-to-digital converter

Design methodology for analog circuit designs using proposed field programmable basic analog building blocks

Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion

High level synthesis of stereo matching: Productivity, performance, and software constraints

Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool

Pipelined high precision beamforming delay calculator for ultrasound imaging

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures

Partial reconfiguration logic synthesis by temporal slicing

Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources

Efficient key-dependent message authentication in reconfigurable hardware

An FPGA-based object detector with dynamic workload balancing

Sharing FPUs in many-soft-cores

Runtime stress-aware replica placement on reconfigurable devices under safety constraints

Efficient region allocation for adaptive partial reconfiguration

SW and HW co-design of Connect6 accelerator with scalable streaming cores

A threat-based Connect6 implementation on FPGA

An FPGA Connect6 Solver with a two-stage pipelined evaluation

An FPGA implementation of a threat-based strategy for Connect6

A Side-Channel hardened IP-Protection Scheme for FPGA-based Platforms

2010 International Conference on Field-Programmable Technology

2009 International Conference on Field-Programmable Technology

2008 International Conference on Field-Programmable Technology

2007 International Conference on Field-Programmable Technology

2006 IEEE International Conference on Field Programmable Technology

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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