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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Krishnamoorthy, R. Fujita, M. Varadarajan, K. Nandy, S.K. |
| Copyright Year | 2011 |
| Description | Author affiliation: Dept. of Electronic Engineering, University of Tokyo, Tokyo, Japan (Krishnamoorthy, R.; Fujita, M.) || CAD Lab, SERC, Indian Institute of Science, Bangalore, India (Varadarajan, K.; Nandy, S.K.) |
| Abstract | Mapping applications onto a Coarse Grained Re-configurable Architecture (CGRA) requires knowledge about the interconnect topology used on the reconfigurable fabric. In order to make communication as efficient as possible, the application sub-structures or partitions need to be mapped to appropriate Compute Elements on the fabric, such that frequently communicating nodes are placed closer. In this paper, we present an interconnect-topology independent mapping algorithm to map applications onto a Coarse Grained Reconfigurable Architecture (CGRA). Our study has been carried out on a CGRA called REDEFINE. The mapping algorithm takes into account the communication serialization which occurs when two data transfers are assigned to the same communication link on the fabric. We extend the algorithm to also address reconfiguration overheads while performing the mapping. The resultant mapping algorithm performs 20% better on average than the mapping scheme based on Baba et al. scheme [1]. |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 273926 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781457717413 |
| e-ISBN | 9781457717406 |
| DOI | 10.1109/FPT.2011.6132677 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-12 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Content Type | Text |
| Resource Type | Article |
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