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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhanpeng Jin Cheng, A.C. |
| Copyright Year | 2011 |
| Description | Author affiliation: Architecture & Systems, Nokia Research Center, Berkeley, CA 94704 (Cheng, A.C.) || Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, NY 13902-6000 (Zhanpeng Jin) |
| Abstract | Artificial Neural Networks (ANN) have proven to be effective in solving various emerging biomedical applications through specialized ANN hardware. Unfortunately, these ANN-based biomedical systems are increasingly vulnerable to both transient and permanent faults, potentially imposing serious threats to human well-being. Inspired by the self-healing and self-recovery mechanisms of the human nervous system, this paper seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework capable of adapting its network structures and operations, both algorithmically and microarchitecturally, to react to unexpected errors. Specifically, we propose three key techniques — Distributed ANN, Neuron Virtualization, and Dual-Layer Checkpointing — to achieve cost-effective structural adaptations and facilitate accurate system recovery. Prototyped and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 819897 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781457717413 |
| e-ISBN | 9781457717406 |
| DOI | 10.1109/FPT.2011.6132669 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-12 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Neurons Artificial neural networks Biological neural networks Synchronization Hardware Training Computer architecture |
| Content Type | Text |
| Resource Type | Article |
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