NDLI: Temporary bonding strength control for self-assembly-based 3D integration

Content Provider	IEEE Xplore Digital Library
Author	Fukushima, T. Ohara, Y. Bea, J. Murugesan, M. Kang-Wook Lee Tanaka, T. Koyanagi, M.
Copyright Year	2011
Description	Author affiliation: New Industry Creation Hatchery Center (NICHe), Tohoku University, 6-6-10, Aza-Aoba, Aramaki, Aoba-ku, Sendai, Miyagi 980-8579, Japan (Fukushima, T.; Bea, J.; Murugesan, M.; Kang-Wook Lee; Koyanagi, M.) \|\| Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University (Ohara, Y.; Tanaka, T.)
Abstract	We have demonstrated bonding strength control for self-assembly-based 3D integration in which many chips are instantly assembled on a wafer all at once by using liquid droplets, and then, temporarily bonded to the wafer. The wafer is named Reconfigured Wafer. The self-assembly-based multichip-to-wafer 3D stacking is called reconfigured-wafer-to-wafer 3D integration. The alignment accuracy is found to be within 1 μm and the temporal bonding strength is well controlled by the quality of oxides as a bonding interface material, liquid types (concentration of additives), total bonding area, and surface roughness of the oxides. The self-assembled and temporarily bonded chips are successfully transferred to another wafer in a face-to-face bonding manner in batch processing.
Starting Page	1
Ending Page	4
File Size	404336
Page Count	4
File Format	PDF
ISBN	9781467321891
e-ISBN	9781467321907
DOI	10.1109/3DIC.2012.6262954
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-31
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Self-assembly Liquids Stacking Surface roughness Rough surfaces Bonding Electron devices
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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