NDLI: 3D stacking using Cu-Cu direct bonding

Content Provider	IEEE Xplore Digital Library
Author	Hu, Y.H. Liu, C.S. Lii, M.J. Rebibis, K.J. Jourdain, A. Manna, A.L. Beyer, G. Beyne, E. Yu, C.H.
Copyright Year	2011
Description	Author affiliation: TSMC, 8, Li-Han Rd. 6, Hsinchu Science Park, 300-77 Hsinchu, Taiwan (Liu, C.S.; Lii, M.J.; Yu, C.H.) \|\| IMEC, Kapeldreef 75, B-3001 Leuven, Belgium (Rebibis, K.J.; Jourdain, A.; Manna, A.L.; Beyer, G.; Beyne, E.) \|\| TSMC assignee at IMEC (Hu, Y.H.)
Abstract	Cu-Cu bonding provides advantages such as cost effective process, fine pitch, and low resistance to advanced 3D IC technology. For 3D stacking, TSV Cu nail can be revealed by wafer backside process and used as interconnect between top and bottom die. No extra process like RDL (Re-Distribution Layer) and bumping are required, thus, μbump pitch is equivalent to TSVs pitch. Further there is no inter-metallic compound (IMC) layer formation and thus improve the mechanical reliability. In this work, we report the results achieved for 3D staking with Cu-Cu bonding by using TCB (Thermal Compression Bonding) process. Three different TSVs nail structures named No Nail, Flat Surface, and Dome Shape, respectively are choose to study the impact of nail structures to various TCB conditions. The TSVs have 5μm diameter with a minimum pitch of 10μm. Cross section SEM (Scanning Electron Microscope) is used to identify interface-bonding qualities. Electrical characterizations on TSV chains are also performed. Based on above specifics results, a best performing structure for TSVs nails is selected in term of electrical connections and good adhesions between dies. Finally, we propose some suggestions for future work on Cu-Cu bonding.
Starting Page	1
Ending Page	4
File Size	315107
Page Count	4
File Format	PDF
ISBN	9781467321891
e-ISBN	9781467321907
DOI	10.1109/3DIC.2012.6262944
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-31
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in