NDLI: Pathfinder 3D: A flow for system-level design space exploration

Content Provider	IEEE Xplore Digital Library
Author	Priyadarshi, S. Jianchen Hu Won Ha Choi Melamed, S. Xi Chen Davis, W.R. Franzon, P.D.
Copyright Year	2011
Description	Author affiliation: Dept. of Electrical and Computer Engineering, North Carolina State University, Box 7911, Raleigh, NC, 27695, USA (Priyadarshi, S.; Jianchen Hu; Won Ha Choi; Melamed, S.; Xi Chen; Davis, W.R.; Franzon, P.D.)
Abstract	Three dimensional integration technology has the potential to provide enhanced performance and device density gains beyond that available from technology scaling alone. However, it provides plethora of design choices for system designers. The full exploitation of the benefits of 3D integration requires a system-level exploration flow which can facilitate in finding an optimal 3D design by comparing possible early design choices. In this paper we present a flow for fast system-level exploration useful for path finding studies. The flow enables users to explore the tradeoff between different stacking and partitioning schemes in terms of performance, power, and temperature. We also present a free open source design kit compiler, FreePDK3D45 and a tool for fast floorplan evaluation of TSV-based digital architectures, Pathfinder3D. The open source design kit and architecture evaluator can help the community to research, learn and explore the various aspects of 3D integration. Using the proposed flow and design kit, we present a case study of 3D integration of a Network on Chip. This case study demonstrates system-level comparisons of the performance, power and temperature of different homogenously partitioned stacking schemes.
Starting Page	1
Ending Page	8
File Size	489851
Page Count	8
File Format	PDF
ISBN	9781467321891
e-ISBN	9781467321907
DOI	10.1109/3DIC.2012.6262961
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-31
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Heating Stacking Materials Conductivity Routing IP networks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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