NDLI: A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors

Content Provider	IEEE Xplore Digital Library
Author	Suarez, M. Brea, V.M. Pardo, F. Carmona-Galan, R. Rodriguez-Vazquez, A.
Copyright Year	2011
Description	Author affiliation: Institute de Microelectrónica de Sevilla (IMSE-CNM), CSIC, Universidad de Sevilla, Sevilla, Spain (Carmona-Galan, R.; Rodriguez-Vazquez, A.) \|\| Centro de Investigation en Tecnologías de la Información, (CITIUS), University of Santiago de Compostela, Santiago de Compostela, Spain (Suarez, M.; Brea, V.M.; Pardo, F.)
Abstract	This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which in turn can be used for operations like object detection, image registration or tracking. The top tier of the architecture contains the image acquisition circuits in an array of 320 × 240 active photodiode sensors (APS) driving a smaller array of 160 × 120 analog processors for low-level image processing. The top tier comprises in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel Analog to Digital Converter (ADC). The reuse of circuits for different functions permits to have a small area for every pixel. The bottom tier of the architecture contains a frame buffer with a set of registers acting as a frame-buffer with a one-to-one correspondence with the analog processors in the top tier, the digital circuitry necessary for the extrema detection and the calculation of the first and second spatial derivatives in the image, as well as Harris and Hessian point detectors. For the time being, a behavioral model of the first tier including mismatch and feedthrough and charge injection errors is discussed. Also, a VHDL model for the bottom tier is addressed. The two-tier architecture is conceived for its implementation on the 130 nm CMOS-3D technology from Tezzaron. A companion chip will perform the higher-level operations as well as communications. In this technology an area of 300 $μm^{2}$ per analog processor has been estimated. The architecture proposed for pyramid generation lets a frame rate of 180 frames/s for an ADC conversion time of 120 μs. The architecture has been proved with object detection for a given feature detector.
Starting Page	1
Ending Page	8
File Size	671756
Page Count	8
File Format	PDF
ISBN	9781467321891
e-ISBN	9781467321907
DOI	10.1109/3DIC.2012.6263019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-31
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Switched capacitor networks Capacitors Detectors Feature extraction Registers Kernel
Content Type	Text
Resource Type	Article

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