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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ivankovic, A. Van der Plas, G. Moroz, V. Choi, M. Cherman, V. Mercha, A. Marchal, P. Gonzalez, M. Eneman, G. Zhang, W. Buisson, T. Detalle, M. Manna, A.L. Verkest, D. Beyer, G. Beyne, E. Vandevelde, B. De Wolf, I. Vandepitte, D. |
| Copyright Year | 2011 |
| Description | Author affiliation: Synopsis, Mountain view, CA, USA (Moroz, V.; Choi, M.) || IMEC, Kapeldreef 75, 3000 Leuven, Belgium (Ivankovic, A.; Van der Plas, G.; Cherman, V.; Mercha, A.; Marchal, P.; Gonzalez, M.; Eneman, G.; Zhang, W.; Buisson, T.; Detalle, M.; Manna, A.L.; Verkest, D.; Beyer, G.; Beyne, E.; Vandevelde, B.; De Wolf, I.) || Katholieke Universiteit Leuven, Oude markt 13, 3000 Leuven, Belgium (Vandepitte, D.) |
| Abstract | Besides the stress around Cu TSV's, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks. |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 783409 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467321891 |
| e-ISBN | 9781467321907 |
| DOI | 10.1109/3DIC.2012.6262972 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-01-31 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Temperature measurement Silicon Arrays Finite element methods Stress FETs |
| Content Type | Text |
| Resource Type | Article |
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