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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kunhyuk Kang Park, S.P. Roy, K. Alam, M.A. |
| Copyright Year | 2007 |
| Description | Author affiliation: Purdue Univ., Lafayette (Kunhyuk Kang; Park, S.P.; Roy, K.; Alam, M.A.) |
| Abstract | Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub-100 nm technologies. So far, studies of NBTI and its impact on circuit performance have assumed an average behavior of the degradation process. However, in very short channel devices, finite number of Si-H bonds in the channel can induce a statistical random variation of the degradation process. This results in significant random Vt variations in PMOS transistor. The NBTI induced variation depends on operating temperature and the effective stress period for the specific device. In this paper, we analyze the impact of stochastic temporal NBTI variations and propose a compact circuit level Vt model. Using the proposed model, we show how temporal Vt variations can affect the lifetime performance of different circuit topologies including 6T SRAM cell and random combinational logic circuits. |
| Starting Page | 730 |
| Ending Page | 734 |
| File Size | 1215489 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424413812 |
| ISSN | 10923152 |
| DOI | 10.1109/ICCAD.2007.4397352 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-11-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Life estimation Lifetime estimation Niobium compounds Titanium compounds Degradation Circuit optimization MOSFETs Negative bias temperature instability Temperature dependence Stress |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Software |
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