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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chih-Chun Lee Jiang, J.-H.R. Chung-Yang Huang Mishchenko, A. |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Taiwan Univ., Taipei (Chih-Chun Lee; Jiang, J.-H.R.; Chung-Yang Huang) |
| Abstract | Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions $\{g_{1},$ ..., $g_{n}),$ i.e. f = $h(g_{1},$ ..., $g_{n}).$ It plays an important role in many aspects of electronic design automation (EDA), ranging from logic synthesis to formal verification. Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper proposes a novel reformulation that extensively exploits the capability of modern satisfiability (SAT) solvers. Thereby, functional dependency is detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The main strengths of the proposed approach include: (1) fast detection of functional dependency with modest memory consumption and thus scalable to large designs, (2) a full capacity to handle a large set of base functions and thus discovering dependency whenever exists, and (3) potential application to large-scale logic optimization and verification reduction. Experimental results show the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS89 and ITC99 benchmark circuits with up to 200 K gates. |
| Starting Page | 227 |
| Ending Page | 233 |
| File Size | 1606011 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781424413812 |
| ISSN | 10923152 |
| DOI | 10.1109/ICCAD.2007.4397270 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-11-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Interpolation Boolean functions Data structures Binary decision diagrams Electronic design automation and methodology Formal verification Circuit synthesis Space technology Logic design Explosions |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Software |
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