NDLI: Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling

Content Provider	IEEE Xplore Digital Library
Author	Guo Yu Peng Li
Copyright Year	2007
Description	Author affiliation: Texas A&M Univ., College Station (Guo Yu; Peng Li)
Abstract	Automated circuit optimization is an important component of complex analog integrated circuit design. Today's analog designs must be optimized not only for nominal performance but also for robustness in order to maintain a reasonable yield with highly scaled VLSI technologies. The complex nature of analog/mixed-signal systems, however, makes this yield-aware analog circuit optimization extremely difficult and costly. In this paper, we adopt a geostatistics motivated approach (i.e. Kriging model) for efficient extraction of yield-aware Pareto front performance models for analog circuits. An iterative search based optimization approach is proposed to efficiently seek optimal performance tradeoffs under yield constraints in high-dimensional design parameter and process variation spaces. Our experiments confirm that the generated yield-aware Pareto fronts are accurate and the optimization procedure is very efficient. The latter is achieved by the well controlled iterative update scheme in the presented techniques which avoids an excessive number of time consuming transistor-level simulations.
Starting Page	464
Ending Page	469
File Size	1028460
Page Count	6
File Format	PDF
ISBN	9781424413812
ISSN	10923152
DOI	10.1109/ICCAD.2007.4397308
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit yield Analog integrated circuits Integrated circuit modeling Design optimization Analog circuits Circuit optimization Robustness Very large scale integration Integrated circuit technology Iterative methods
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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