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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Elloumi, Y. Akil, M. Grandpierre, T. Bedoui, M. |
| Copyright Year | 2010 |
| Description | Author affiliation: Université Paris-Est, ESIEE Paris, Laboratoire d'Informatique Gaspard Monge, Equipe A3SI, 93162 Noisy le Grand Cedex, France (Elloumi, Y.; Akil, M.; Grandpierre, T.) || University of Monastir, Faculty of Medicine of Monastir, Laboratory of Biophysics, TIM Team, 5019, Tunisia (Bedoui, M.) |
| Abstract | Field Programmable Gate Arrays (FPGA) are flexible, so they are commonly used in many high speed applications. However, power constraints are the most important limiting factors while implementing high speed adaptable applications. This work addresses the optimization of the execution time and power consumption. We propose a new design methodology by extending Algorithm-Architecture-Adequacy (AAA) methodology. It provides an implementation which meets real time constraints and allows the designer to optimize power consumption or material resources. The extension has been implemented in AAA software tool called Synchronized Distributed Executive for Integrated Circuits (SynDEx-IC). The experimental results show that the mentioned software tool provides an architecture that consumes less power among the explored ones, which the average power is reduced by 15.75%. |
| Starting Page | 639 |
| Ending Page | 642 |
| File Size | 537858 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424481552 |
| e-ISBN | 9781424481576 |
| DOI | 10.1109/ICECS.2010.5724593 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-12 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Performance evaluation power consumption design methodology optimization estimation heuristic |
| Content Type | Text |
| Resource Type | Article |
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