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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Motten, A. Claesen, L. |
| Copyright Year | 2010 |
| Description | Author affiliation: Expertise Centre for Digital Media, Hasselt University - tUL - IBBT, Wetenschapspark 2, 3590 Diepenbeek, Belgium (Motten, A.; Claesen, L.) |
| Abstract | This paper presents a novel parallel System-on-Chip (SoC) memory architecture for a stereo vision system as required in 3D TV applications. It allows for a parallel access to all pixels located in a chosen window of the image. Using this architecture a complete window refresh on each clock cycle is possible, which can be used to increase the depth range of a stereo vision algorithm. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. Hardware resource utilization for different processor window size configurations is compared based on FPGA logic element use. |
| Starting Page | 495 |
| Ending Page | 498 |
| File Size | 839821 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424481552 |
| e-ISBN | 9781424481576 |
| DOI | 10.1109/ICECS.2010.5724557 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-12 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Arrays Clocks Field programmable gate arrays Image segmentation FPGA component Parallel memory architecture stereo matching computer vision system-on-chip |
| Content Type | Text |
| Resource Type | Article |
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