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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hartmann, S. Schiefer, S. Scholze, S. Partzsch, J. Mayr, C. Henker, S. Schuffny, R. |
| Copyright Year | 2010 |
| Description | Author affiliation: Endowed Chair for Parallel VLSI Systems and Neural Circuits, Technical University Dresden, Germany (Hartmann, S.; Schiefer, S.; Scholze, S.; Partzsch, J.; Mayr, C.; Henker, S.; Schuffny, R.) |
| Abstract | One of the main challenges in large scale neuromorphic VLSI systems is the design of the communication infrastructure. Traditionally, the neural communication has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of pulses, while the configuration was achieved via off-the-shelf chip connect protocols. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols, as well as an integration of both communication and configuration in the same interface. We present the PCB and FPGA design of such an interface for a newly developed waferscale neuromorphic system. The serial event communication of other current approaches has been refined into a packet based synchronous (rather than asynchronous) protocol, which offers better flexibility and bandwidth utilization. A factor 30–100 greater event transmission rate has been achieved. Compared to other approaches, the full communication bandwidth can also be employed for configuration. The system offers additional functionality, such as event storage and replay. Also, a very high degree of mechanical integration has been achieved. |
| Starting Page | 950 |
| Ending Page | 953 |
| File Size | 1023327 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424481552 |
| e-ISBN | 9781424481576 |
| DOI | 10.1109/ICECS.2010.5724670 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-12 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Connectors Transceivers Indexes Ethernet networks Media Field programmable gate arrays configuration over AER Gigaevent serial AER packet-based AER FPGA event routing |
| Content Type | Text |
| Resource Type | Article |
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