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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mirzaie, H. Khameh, H. Shamsi, H. |
| Copyright Year | 2010 |
| Description | Author affiliation: Dept. of Electrical Engineering, K.N.Toosi University of Technology, Tehran, Iran (Mirzaie, H.; Shamsi, H.) || Dept. of Electrical Engineering, Islamic Azad University Qazvin Branch, Iran (Khameh, H.) |
| Abstract | This paper describes the design and simulation of a new high-gain, low-power two-stage Op-Amp in a 0.18µm CMOS technology. Using both the gate-driven transistor and positive feedback concepts, the DC-gain of the conventional two-stage Op-Amp is increased about 20dB while power dissipation is approximately unchanged. Both the analytical and simulation results show that although the DC-gain will increase about 20dB but no significant change will be made in the unity-gain bandwidth of the circuit. Besides, the settling behavior of the proposed circuit is verified by employing the Op-Amp in a flip-around sample-and-hold. It is shown that the proposed Op-Amp has better settling behavior than its conventional counterpart. |
| Starting Page | 1140 |
| Ending Page | 1143 |
| File Size | 1187448 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424481552 |
| e-ISBN | 9781424481576 |
| DOI | 10.1109/ICECS.2010.5724718 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-12 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology Logic gates CMOS integrated circuits sample-and-hold Op-Amp gate-driven Positive feedback |
| Content Type | Text |
| Resource Type | Article |
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