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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | O'Connor, I. Jabeur, K. Navarro, D. Yakymets, N. Gaillardon, P.E. Ben Jamaa, M.H. Clermidy, F. |
| Copyright Year | 2010 |
| Description | Author affiliation: CEA-LETI-MINATEC, Grenoble, France (Gaillardon, P.E.; Ben Jamaa, M.H.; Clermidy, F.) || Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, Ecully, France (O'Connor, I.; Jabeur, K.; Navarro, D.; Yakymets, N.) |
| Abstract | The back-gate terminal on double-gate ambipolar transistors can be used as a powerful vector to achieve fine-grain logic reconfigurability. This paper describes ways of exploiting this property to improve on standard cell logic techniques, and to build logic gates with tunable functionalities. Given the vastly reduced transistor count, conventional use of reconfigurable interconnect at the cell level would lead to large overhead, and new interconnect strategies are required. We explore two types of interconnect architectures (island-style and cell-matrix) and develop a mapping method to evaluate trade-offs between matrix occupation, cluster size and switch requirements. |
| Starting Page | 66 |
| Ending Page | 69 |
| File Size | 852653 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424481552 |
| e-ISBN | 9781424481576 |
| DOI | 10.1109/ICECS.2010.5724455 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-12 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CNTFETs Measurement reconfigurable architectures nanotechnology logic design |
| Content Type | Text |
| Resource Type | Article |
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