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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Moosazadeh, Tohid Yavari, Mohammad |
| Copyright Year | 2010 |
| Description | Author affiliation: Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran (Moosazadeh, Tohid; Yavari, Mohammad) |
| Abstract | This paper presents a digital background calibration technique for 1.5 bit/stage pipelined analog-to-digital converters. The proposed method corrects for capacitors mismatch, gain error and gain nonlinearities. The new algorithm uses a calibration signal, modified stages and skip-fill method for error calibration while does not require any accurate calibration signal and any added analog circuitry; just a digital finite impulse response filter is needed to implement the polynomial interpolation recovering the skipped samples. The technique is tested on a prototype 12-bit 80-MS/s pipelined ADC which has a capacitors mismatch of 0.1% and 38 dB amplifier DC gain. Simulated in a 90-nm CMOS technology with HSPICE, the ADC achieves 0.25LSB of peak DNL, ±0.25LSB of peak INL, 72dB peak SNDR and 78dB peak SFDR while the core of ADC (without calibration circuitry) consumes only 57.8 mW from a 1V power supply. |
| Starting Page | 126 |
| Ending Page | 129 |
| File Size | 1218939 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424481552 |
| e-ISBN | 9781424481576 |
| DOI | 10.1109/ICECS.2010.5724470 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-12 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Calibration Variable speed drives Artificial neural networks Switches digital background calibration Pipelined ADCs capacitor mismatch gain error amplifier nonlinearity |
| Content Type | Text |
| Resource Type | Article |
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