NDLI: A simple digital background gain error calibration technique for pipelined ADCs

Content Provider	IEEE Xplore Digital Library
Author	Moosazadeh, T. Yavari, M.
Copyright Year	2010
Description	Author affiliation: Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran (Moosazadeh, T.; Yavari, M.)
Abstract	This paper presents a simple digital background calibration technique to eliminate the gain errors of 1.5bit/stage pipelined analog-to-digital converters caused by finite DC gain of stage amplifiers. In this technique, the gain errors are extracted by creating a mismatch between stage sub-ADC threshold voltages in the “split ADC” architecture derived from [1] and [2]. The technique is tested on a prototype 12bit 1.5bit/stage pipelined ADC with maximum 50dB amplifier DC gain. MATLAB and Simulink environment simulations show 19dB SNDR and 45dB SFDR improvements after calibration technique is applied on the first four stages of the ADC, which were limited to 52dB and 55dB before calibration.
Starting Page	437
Ending Page	441
File Size	170979
Page Count	5
File Format	PDF
ISBN	9781424467600
e-ISBN	9781424467600
DOI	10.1109/IRANIANCEE.2010.5507031
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-11
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit synthesis Integrated circuit technology Capacitors Laboratories Split ADC Calibration Analog-digital conversion Prototypes Digital background calibration Pipelined ADCs Threshold voltage Error correction Gain errors Testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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