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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shuli Gao Al-Khalili, D. Chabini, N. |
| Copyright Year | 2009 |
| Description | Author affiliation: Department of ECE, Royal Military College of Canada, Canada (Shuli Gao; Al-Khalili, D.; Chabini, N.) |
| Abstract | In this paper, we present an efficient design approach for the implementation of large size matrix multiplication with wide bit size elements targeting FPGAs. The proposed technique first partitions the input matrices into smaller dimensions, and then segment the word-width of the elements into smaller sections. The segmentation is driven by the architecture of the targeted FPGA platform. A highly optimized scalar signed multiplier has been developed, and used as a basic block to construct a 2 by 2 matrix multiplier on Xilinx' and Altera's FPGAs. The result of the implementations showed that our method has outperformed the techniques utilized by commercial tools, ISE and Quartus, and the balanced word-width decomposition approach to realize the matrix multiplications proposed in [6]. Compared to these approaches we achieved delay reduction range from 7.1% to 28% and area saving range from 6.7% to 32%. |
| Starting Page | 427 |
| Ending Page | 430 |
| File Size | 310446 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450909 |
| DOI | 10.1109/ICECS.2009.5410901 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-13 |
| Publisher Place | Tunisia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Matrix decomposition Field programmable gate arrays Educational institutions Delay Signal processing Arithmetic Signal processing algorithms Design optimization |
| Content Type | Text |
| Resource Type | Article |
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